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Publications

CHES'26
Efficient SIMD Implementation of the BLS Signature Scheme Using Intel AVX-512.
Ganqin Liu, Hao Cheng†, Georgios Fotiadis, Jipeng Zhang, Johann Großschädl.
[paper] [code]
MICRO'26
VAXEN: A Versatile AVX Extension for Zero-Knowledge Proof and Post-Quantum Cryptography.
Jipeng Zhang, Hao Cheng†, Tao Lu, Jiaheng Zhang†.
[paper] [code]
ESORICS'26
Prune to Grow: A Pruning-Driven Framework for MV-PC Side-Channel Attacks against Kyber.
Jinnuo Li, Hao Cheng†, Chi Cheng.
[paper]
CiC'26
Extending RISC-V to Support Flexible-Radix Multiply-Accumulate Operations.
Isaar Ahmad, Hao Cheng†, Johann Großschädl, Daniel Page.
[paper] [code]
Inscrypt'26
Extending MV-PC Side-Channel Attacks to Higher-Order Masked Implementations of Kyber.
Jinnuo Li, Hao Cheng†, Chi Cheng.
CCS'26
MamaBearZKP: A Holistic Co-design of Prime Fields and Proving Stacks for High-Throughput ZKP on Modern CPUs.
Jipeng Zhang, Yanpei Guo, Tao Lu, Hao Cheng, Jiaheng Zhang.
[paper] [code]
Cyber
security'26
Hardware Masking with Buffer Chain.
Guofeng Qin, Yihao Zhu, Chun Guo, Bohan Wang, Hao Cheng, Weijia Wang.
[paper]
ICICS'26
A RISC-V Software Implementation and Instruction Set Extension for PERK.
Yunfei Wang, Hao Cheng, Qi Tian, Weijia Wang, Long Chen.
preprint'26
ISE-supported Erasure of Residual Shares.
Hao Cheng, Linus Mainka, Daniel Page, Kostas Papagiannopoulos.
[paper]
preprint'26
Pilaf: Fully Tight Two-Round Threshold Signatures with Adaptive Corruptions.
Chen Qian, Xingyu Zhao, Hao Cheng, Zengpeng Li, Puwen Wei, Quan Yuan.
[paper]
CHES'25
Fast AVX-512 Implementation of the Optimal Ate Pairing on BLS12-381.
Hao Cheng, Georgios Fotiadis, Johann Großschädl, Daniel Page.
[paper] [slides] [code]
SAC'25
High-Throughput EdDSA Verification on Intel Processors with Advanced Vector Extensions.
Bowen Zhang, Hao Cheng†, Johann Großschädl, Peter Y. A. Ryan.
[paper] [code]
CHES'25
A Code-Based ISE to Protect Boolean Masking in Software.
Qi Tian, Hao Cheng, Chun Guo, Daniel Page, Meiqin Wang, Weijia Wang.
[paper] [slides]
preprint'25
SoK: Instruction Set Extensions for Cryptographers.
Hao Cheng, Johann Großschädl, Ben Marshall, Daniel Page, Markku-Juhani O. Saarinen.
[paper]
CHES'24
eLIMInate: a Leakage-focused ISE for Masked Implementation.
Hao Cheng, Daniel Page, Weijia Wang.
[paper] [slides] [code]
DAC'24
RISC-V Instruction Set Extensions for Multi-Precision Integer Arithmetic.
Hao Cheng, Georgios Fotiadis, Johann Großschädl, Daniel Page, Thinh Pham, Peter Y. A. Ryan.
[paper] [slides] [poster] [code]
CHES'23
RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography.
Hao Cheng, Johann Großschädl, Ben Marshall, Daniel Page, Thinh Pham.
[paper] [slides] [code]
MSPN'23
IoTDisco: Strong yet Lightweight End-to-End Security for the Internet of Constrained Things.
Hao Cheng, Georgios Fotiadis, Johann Großschädl, Peter Y. A. Ryan.
[paper] [code]
CHES'22
Highly Vectorized SIKE for AVX-512.
Hao Cheng, Georgios Fotiadis, Johann Großschädl, Peter Y. A. Ryan.
[paper] [slides] [code]
SecITC'22
Lightweight Permutation-Based Cryptography for the Ultra-Low-Power Internet of Things.
Malik Alsahli, Alex Borgognoni, Luan Cardoso dos Santos, Hao Cheng, Christian Franck, Johann Großschädl.
[paper] [code]
CHES'21
Batching CSIDH Group Actions using AVX-512.
Hao Cheng, Georgios Fotiadis, Johann Großschädl, Peter Y. A. Ryan, Peter B. Rønne.
[paper] [slides] [code]
DATE'21
AVRNTRU: Lightweight NTRU-Based Post-Quantum Cryptography for 8-bit AVR Microcontrollers.
Hao Cheng, Johann Großschädl, Peter B. Rønne, Peter Y. A. Ryan.
[paper] [slides] [code]
SAC'20
High-Throughput Elliptic Curve Cryptography Using AVX2 Vector Instructions.
Hao Cheng, Johann Großschädl, Jiaqi Tian, Peter B. Rønne, Peter Y. A. Ryan.
[paper] [slides] [code]
CARDIS'20
Lightweight Post-Quantum Key Encapsulation for 8-bit AVR Microcontrollers.
Hao Cheng, Johann Großschädl, Peter B. Rønne, Peter Y. A. Ryan.
[paper] [slides]
WISTP'19
A Lightweight Implementation of NTRU Prime for the Post-Quantum Internet of Things.
Hao Cheng, Daniel Dinu, Johann Großschädl, Peter B. Rønne, Peter Y. A. Ryan.
[paper] [slides]
SecITC'18
Efficient Implementation of the SHA-512 Hash Function for 8-bit AVR Microcontrollers.
Hao Cheng, Daniel Dinu, Johann Großschädl.
[paper]